IEEE 802.3af/at-Compliant, Powered Device Interface
Controllers with Integrated Power MOSFET
_______________________________________________________________________________________ 7
  Pin Description
PIN
NAME
FUNCTION
1
N.C.
No Connection. Not internally connected.
2
V
DD
 
Positive Supply Input. Connect a 68nF (min) bypass capacitor between V
DD
 and V
SS
.
3
DET
Detection Resistor Input. Connect a signature resistor (R
DET
 = 24.9kI) from DET to V
DD
.
4
I.C.
Internally Connected. Leave unconnected.
5, 6
V
SS
Negative Supply Input. V
SS
 connects to the source of the integrated isolation n-channel power MOSFET.
7, 8
RTN
Drain of Isolation MOSFET. RTN connects to the drain of the integrated isolation n-channel power
MOSFET. Connect RTN to the downstream DC-DC converter ground as shown in the Typical Application
Circuit.
9
WAD
Wall Power Adapter Detector Input. Wall adapter detection is enabled the moment V
DD
 - V
SS
 crosses
the mark event threshold. Detection occurs when the voltage from WAD to RTN is greater than 9V. When
a wall power adapter is present, the isolation n-channel power MOSFET turns off, 2EC current sink turns
on. Connect WAD directly to RTN when the wall power adapter or other auxiliary power source is not
used.
10
PG
Open-Drain Power-Good Indicator Output. PG sinks 230FA to disable the downstream DC-DC converter
while turning on the hot-swap MOSFET switch. PG current sink is disabled during detection, classifica-
tion, and in the steady-state power mode. The PG current sink is turned on to disable the downstream
DC-DC converter when the device is in sleep mode.
  Pin Configuration
3
4
2
1
10
9
11
EP*
5
6
V
DD
8
16
15
13
DET
I.C.
CLS
2EC
PG
WAD
MAX5981A
MAX5981B
7
14
N.C.
TQFN
12
CONNECT TO V
SS
.
+
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